1. Field of the Invention
The invention relates to bridge devices in multicontroller computer applications, and more particularly, to improving bus utilization efficiency during data transfer operations among the system controllers.
2. Description of the Related Art
Inclusion of multiple microcontroller devices within a single application specific integrated circuit (ASIC) has become common place. As the size of ASIC computer chips decrease and system speeds increase, system efficiency is scrutinized at every level. Communications among the multiple controllers in a system or on an ASIC present one part of the larger computer system efficiently that ultimately affects overall system speed. Data transfer, including read and write operations to system memory and even among the ASIC controllers, are required to be efficient or risk choking overall system speeds as devices wait for bus operations to catch up to internal processes. To make matters more complex, the various controllers and the system memory often reside on multiple computer communications buses. As such, bridge-type devices have become a common component to facilitate data transfers among the different bus interfaces. However, xe2x80x9cdumbxe2x80x9d bridges serve to introduce additional latencies without efficiency improvement.
For many reasons, maintaining alignment with cache line boundaries has become important to improve efficiencies. For example, memory controllers are generally more efficient in responding to write operations when they operate on cache line boundaries (i.e. receive data in amounts equal to a cache line and aligned with its cache boundaries). In addition, the Peripheral Component Interconnect (PCI) computer bus standard requires certain bus management techniques regarding cache line amounts of data. For example, PCI provides for at least two types of write operations: memory write (MW) and memory write invalidate (MWI). However, these operations require entire cache line operations or multiples thereof. One approach for operating on a cache-line basis has involved preconfiguring all system write operations to occur on a cache-line multiple basis. Such configuration, however, has ignored certain device limitations such as buffering capabilities. Specifically, where the rate of incoming data flow exceeds the rate of outgoing data, buffer capacity can be exceeded causing a forced disconnect of the write initiating device. Other common situations are prone to cause cache line misalignment. One situation is where the write initiating device begins at a cache line boundary. If the amount of receiving buffer space available is not a multiple of the cache line size, then the write initiating device may be disconnected at some point in the middle of the write operation irrespective of cache line alignment. A second situation exists where the write initiating device will begin a write operation at a non-aligned address, but transfer an amount of data that is a multiple of a cache line size. In this situation, because the write operation has completed, the write initiating device will then be disconnected, leaving the end data written in between cache line boundaries.
The bridge device according to the present invention maintains cache line alignment during write operations between the bridged devices. Specifically, after a write command is issued by a device, the device continues to write to a write buffer until the capacity of the write buffer approaches a full capacity. As the data in the buffer accumulates to ward a full capacity, an additional amount of write data is calculated based on the space available in the write buffer, the starting address of the write operation and the cache line such that the write initiating device is disconnected with its write data ending on a cache line boundary in memory.